Power supplies play an essential part in system applications. A quality Power supply PCB design can optimize power efficiency, ease heat dissipation pressure and lower noise emissions for increased accuracy and stability in power outdoor. At present, numerous product applications such as industrial, automotive, communications and consumer have demanded miniaturized solutions; as a result, miniaturization requirements have also increased accordingly. This article will explore the PCB layout of power supplies details.
The Fundamental Principles of Power Supply PCB Layout.
Locating of Power Source
First and foremost, when considering power supplies PCB at an early stage of system layout, their location must be taken into account. A key principle is placing them near their load to avoid PCB traces being too long and creating too great of a voltage differential between actual load voltage and set output voltage set by power supplies resulting in inaccurate voltage measurement, slower dynamic load response, reduced efficiency. Furthermore, an estimate of power supply area must also be provided; otherwise many PCB layout guidelines cannot be followed and working performance cannot be guaranteed for these power supplies.
At the same time, if a system features a fan for heat dissipation, positioning its power supply near its air outlet will help dissipate heat more effectively while increasing power efficiency. To ensure effective fan cooling, its heat dissipation path must also be carefully considered so as to avoid blocking tall passive components (inductors and electrolytic capacitors) from impeding short active components like MOS tubes and PWM controllers from dissipating heat effectively.
Multilayer PCB Design Process
As part of multilayer PCB board design, it is often advised to add a ground or DC voltage layer as a shielding layer between high current layers (such as input voltage or output voltage ) and sensitive small signal layers. A ground layer or DC voltage layer can effectively isolate sensitive small signals and power loops to avoid interference with small signals. When designing the ground or DC voltage layer layout, minimizing wiring to ensure an uninterrupted layer is a priority if possible.
When necessary make sure lines follow in the same direction as high-current wiring of power layers to minimize interference with small signals. If there must be wiring in addition to follow similar high current wiring of power layers so as to reduce interference between them both.For example:
Option 1(ineffective design)
6-қабати PCB
Layer 1: Power Device
Layer 2: Small Signal
Level 3: Ground level
Layer 4: DC voltage or floor layer
Layer 5: Small Signal
Layer 6: Power device or controller
4-қабати PCB
Layer 1: Power Device
Layer 2: Small Signal
Level 3: Ground level
Layer 4: Small signal or controller
Option 2(effective design)
6-қабати PCB
Layer 1: Power Device
Level 2: Ground level
Layer 3: Small Signal
Layer 4: DC voltage or floor layer
Layer 5: Small Signal
Layer 6: Power device or controller
4-қабати PCB
Layer 1: Power Device
Level 2: Ground level
Layer 3: Small Signal
Layer 4: Small signal or controller
Optional 1 is an ineffective design wherein the small signal layer is trapped between ground and high current layers, increasing capacitive coupling between it and high current layers and consequently making interference between small signals easily interferable with high current layers more likely.
Power device layout
A switching power supply circuit consists of two loops – the power loop and small signal control loop. In the power loop are devices which carry large currents such as inductors, capacitors and MOS transistors – these devices must be laid out before beginning. Meanwhile, small signal control loop features feedback resistors, compensation networks, frequency settings and overcurrent settings, typically located on specific locations on a power chip.
Calculation of Power Line Width
Due to the magnitude of current flowing through power lines, narrowed lines will result in increased losses and PCB temperatures.
Perfect for line width calculations between 1A to 20A with currents, where W is line width measured in mils; I is current measured in Amperes; Tcu is copper weight in OZs of PCB copper material weighing in OZs.
Assuming 5A current and 1Oz copper weight as an example, minimum line width required would be 120mils.
Here is the empirical formula for line width:
Loop Layout with High Current Change Rate
All components, such as PCB traces, contain parasitic inductance, capacitance and resistance, which will fluctuate with changes in current. A sudden current change can result in voltage spikes on parasitic inductance, which exceed the withstand voltage requirements and spread interference outwards further reducing chances of passing an EMI test.
Figure 1 Shown is the basic structure of a Buck circuit.
Figure 1 depicts the basic structure of a Buck circuit. First, green lines indicate where current flows when the upper tube is turned on; red lines represent the current paths when its turned off; loops with high current change rates have only one color to signify their part in the circuit – this method applies to all circuit topologies.
Figure 2. Buck circuit for high current change rate loop
Figure 2 depicts the high current change rate loop of a Buck circuit, with blue representing its high current change rate loop. It is necessary to ensure that its ground and plane are kept separate; its decoupling capacitors typically range in value between 0.1uF to 10uF; they are ceramic capacitors of type X5R or X7R type with small parasitic inductance and resistance characteristics that provide good current flow path at high current change rates.
Figure 3 Outline of Boost Circuit
Figure 4. Boost circuit for large current change rate loop
Like its counterpart, the Boost circuit can be analysed and designed using the same method as used with Buck circuits (Figures 3 and 4 respectively show basic circuit structure of Boost circuit and large current change rate loop).
High Voltage Change Rate Node Layout
Switching power supplies have nodes between switching tube MOSs and freewheeling diodes (or MOS tube-rectifiers) that switch quickly between ground voltage and high voltage and their voltage change rate is rapid; their node voltage, known as “ringing voltage”, is the source of most electromagnetic interference noise (EMI).
To minimize coupling with noise-sensitive small signal lines, the area around switch nodes must be minimized, but keep in mind this node cannot become too small!
Figure 5. SCT2360 Load Schematic Diagram 12V input 5V output 6A schematic
So in multi-layer board designs, it is beneficial to include a ground plane on the next layer from a switch node for enhanced isolation and reduced noise propagation.
SCT2360 serves as an example in which L1 and SW are situated relatively closely; heat dissipation through copper nodes should be maximized in order to reduce propagation ability of noise propagation. Eashub has taken this problem into consideration when designing their chip, so as to minimize loop connections between BST and SW (ie on adjacent pins).
Figure 6SCT2360 Layout
High-frequency Filter Capacitor Layout.
High-frequency filter capacitors are an essential part of any electronic system, serving to protect from large current change rate loops and reduce voltage stress. On SCT2360 for instance, capacitor C3 is located closest to both VIN PIN and PGND PIN of the chip via a short but thick connection line.
Table 2 provides an example of high-frequency filter capacitor layout (no vias).
Table 3 Shown below is an example of high-frequency filter capacitor layout (with vias).
Multiple power layouts
If multiple power supplies sharing an input source within a system don’t operate synchronously with each other, their input power supply traces must be separated in order to prevent common mode noise between these supplies from propagating to both input and ground and interfering with one another.
Table 4 Provides examples of multipower supply configuration.
хулоса:
An estimated 80% of power supply PCB design issues originate in PCB layout. Dedicating adequate time in PCB layout early can significantly decrease debugging time later and shorten development cycles, SCT23xx series products offering chip PIN pin optimization can assist customers in reaching optimal PCB layout for best power performance.
Эашуб strives to deliver outstanding power chip details, and continues to create top-quality power chip products to provide customers with optimal solutions.
